Publication detail

Methodology of Selecting Scan-Based Testability Improving Technique

KOTÁSEK, Z., STRNADEL, J., PEČENKA, T.

Original Title

Methodology of Selecting Scan-Based Testability Improving Technique

Type

conference paper

Language

English

Original Abstract

In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.

Keywords

design for testability, scan method, testable core

Authors

KOTÁSEK, Z., STRNADEL, J., PEČENKA, T.

RIV year

2005

Released

19. 4. 2005

Publisher

University of West Hungary

Location

Sopron

ISBN

963-9364-48-7

Book

Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop

Pages from

186

Pages to

189

Pages count

4

URL

http://www.fit.vutbr.cz/~pecenka/pubs/2005_ddecs_scan.pdf

BibTex

@inproceedings{BUT21466,
  author="Zdeněk {Kotásek} and Josef {Strnadel} and Tomáš {Pečenka}",
  title="Methodology of Selecting Scan-Based Testability Improving Technique",
  booktitle="Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  year="2005",
  pages="186--189",
  publisher="University of West Hungary",
  address="Sopron",
  isbn="963-9364-48-7",
  url="http://www.fit.vutbr.cz/~pecenka/pubs/2005_ddecs_scan.pdf"
}