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Publication detail
ŠKARVADA, J.
Original Title
Test Scheduling for SOC under Power Constraints
Type
conference paper
Language
English
Original Abstract
The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.
Keywords
test scheduling, power constraint, test application conflict graph, genetic algorithm
Authors
RIV year
2006
Released
20. 4. 2006
Publisher
Czech Technical University Publishing House
Location
Prague
ISBN
1-4244-0184-4
Book
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pages from
91
Pages to
93
Pages count
3
BibTex
@inproceedings{BUT22187, author="Jaroslav {Škarvada}", title="Test Scheduling for SOC under Power Constraints", booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems", year="2006", pages="91--93", publisher="Czech Technical University Publishing House", address="Prague", isbn="1-4244-0184-4" }