Publication detail

On Distribution of Testability Values in Scan-Layout State-Space

STRNADEL, J.

Original Title

On Distribution of Testability Values in Scan-Layout State-Space

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout, the better testability properties correspond to the scan-layout.

Keywords

digital circuit diagnostics, register-transfer level, circuit data-path, testability analysis, design for testability, testability improvements, scan technique

Authors

STRNADEL, J.

RIV year

2006

Released

19. 9. 2006

Publisher

The University of Technology Košice

Location

Košice

ISBN

80-8073-598-0

Book

Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics

Pages from

308

Pages to

313

Pages count

6

URL

https://www.fit.vut.cz/research/publication/8181/

BibTex

@inproceedings{BUT22271,
  author="Josef {Strnadel}",
  title="On Distribution of Testability Values in Scan-Layout State-Space",
  booktitle="Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics",
  year="2006",
  pages="308--313",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-8073-598-0",
  url="https://www.fit.vut.cz/research/publication/8181/"
}

Documents

2006-eci.pdf