Publication detail

Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

KUBÍČEK, M.

Original Title

Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals

Type

conference paper

Language

English

Original Abstract

The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.

Keywords

Simulation, Software data recovery, VHDL-AMS

Authors

KUBÍČEK, M.

RIV year

2007

Released

1. 1. 2007

Publisher

MJ servicsBožetěchova 133, 612 00 Brno, Czech Republic

Location

Department of Radio Electronics, Brno University of TechnologyPurkyňova 118, 612 00 Brno, Czech Republic

ISBN

978-1-4244-0821-4

Book

Proceedings of 17th International Conference Radioelektronika 2007

Pages from

211

Pages to

214

Pages count

4

BibTex

@inproceedings{BUT22609,
  author="Michal {Kubíček}",
  title="Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals",
  booktitle="Proceedings of 17th International Conference Radioelektronika 2007",
  year="2007",
  pages="211--214",
  publisher="MJ servicsBožetěchova 133, 612 00 Brno, Czech Republic",
  address="Department of Radio Electronics, Brno University of TechnologyPurkyňova 118, 612 00 Brno, Czech Republic",
  isbn="978-1-4244-0821-4"
}