Publication detail

Combinational Divider in FPGA

KOLOUCH, J.

Original Title

Combinational Divider in FPGA

Type

conference paper

Language

English

Original Abstract

The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.

Keywords

arithmetic functions, combinational logic, integer division, synthesis, FPGA, propagation delay, resource consumption

Authors

KOLOUCH, J.

RIV year

2007

Released

24. 4. 2007

Publisher

Brno University of Technology

Location

Brno

ISBN

1-4244-0821-0

Book

Proceedings of 17th International Conference Radioelektronika 2007

Pages from

69

Pages to

73

Pages count

4

BibTex

@inproceedings{BUT23624,
  author="Jaromír {Kolouch}",
  title="Combinational Divider in FPGA",
  booktitle="Proceedings of 17th International Conference Radioelektronika 2007",
  year="2007",
  pages="69--73",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="1-4244-0821-0"
}