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Publication detail
ŠEBESTA, J.
Original Title
Discrete-time Phase and Delay Locked Loops Analyses in Tracking Mode
Type
conference paper
Language
English
Original Abstract
Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.
Keywords
Carrier synchronization, Coherent demodulation, Software defined receiver, Symbol timing
Authors
RIV year
2007
Released
22. 11. 2007
Publisher
WASET
Location
Venice, Italia
Pages from
181
Pages to
185
Pages count
4
BibTex
@inproceedings{BUT23944, author="Jiří {Šebesta}", title="Discrete-time Phase and Delay Locked Loops Analyses in Tracking Mode", booktitle="Proceedings of World Academy of Science, Engineering, and Technology - IV. International Conference on Computer, Electrical, and System Science, and Engineering CESSE 2007, Venice, Italy, November 23-25, 2007", year="2007", series="1", number="1", pages="181--185", publisher="WASET", address="Venice, Italia" }