Publication detail

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L.

Original Title

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

TBD

Keywords

digital circuit, polymorphic gate, adder, testing

Authors

SEKANINA, L.

RIV year

2007

Released

19. 4. 2007

Publisher

IEEE Computer Society

Location

Gliwice

ISBN

1424411610

Book

2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Pages from

243

Pages to

246

Pages count

4

URL

http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf

BibTex

@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="243--246",
  publisher="IEEE Computer Society",
  address="Gliwice",
  isbn="1424411610",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs07/ddecs07.pdf"
}