Publication detail

Test Controller Synthesis Constrained by Circuit Testability Analysis

RŮŽIČKA, R. STRNADEL, J.

Original Title

Test Controller Synthesis Constrained by Circuit Testability Analysis

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.

Keywords

testability analysis, test controller, RTL digital circuit diagnostics

Authors

RŮŽIČKA, R.; STRNADEL, J.

RIV year

2007

Released

29. 8. 2007

Publisher

IEEE Computer Society Press

Location

Los Alamitos

ISBN

0-7695-2978-X

Book

Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

Pages from

626

Pages to

633

Pages count

8

BibTex

@inproceedings{BUT28840,
  author="Richard {Růžička} and Josef {Strnadel}",
  title="Test Controller Synthesis Constrained by Circuit Testability Analysis",
  booktitle="Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools",
  year="2007",
  pages="626--633",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos",
  isbn="0-7695-2978-X"
}