Publication detail

Physical Demonstration of Polymorphic Self-checking Circuits

RŮŽIČKA, R. SEKANINA, L. PROKOP, R.

Original Title

Physical Demonstration of Polymorphic Self-checking Circuits

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.

Keywords

digital circuit, polymorphic gate, self-checking, adder

Authors

RŮŽIČKA, R.; SEKANINA, L.; PROKOP, R.

RIV year

2008

Released

15. 7. 2008

Publisher

IEEE Computer Society

Location

Los Alamitos

ISBN

978-0-7695-3264-6

Book

Proc. of the 14th IEEE Int. On-Line Testing Symposium

Pages from

31

Pages to

36

Pages count

6

URL

https://www.fit.vut.cz/research/publication/8652/

BibTex

@inproceedings{BUT30488,
  author="Richard {Růžička} and Lukáš {Sekanina} and Roman {Prokop}",
  title="Physical Demonstration of Polymorphic Self-checking Circuits",
  booktitle="Proc. of the 14th IEEE Int. On-Line Testing Symposium",
  year="2008",
  pages="31--36",
  publisher="IEEE Computer Society",
  address="Los Alamitos",
  isbn="978-0-7695-3264-6",
  url="https://www.fit.vut.cz/research/publication/8652/"
}

Documents

ruzicka-polymorph.pdf