Publication detail

Power Conscious RTL Test Scheduling

ŠKARVADA, J. KOTÁSEK, Z. HERRMAN, T.

Original Title

Power Conscious RTL Test Scheduling

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, a methodology for power conscious RTL test scheduling is presented. At first the circuit under analysis (CUA) is mapped into technological library and partitioned. For each partition the sequences of test vectors are generated and if possible also reordered in order to reduce power consumption during the test application. For the test scheduling the Integer Linear Programming (ILP) model is used. The goal of the methodology is to find the test schedule with lowest test application time and with power consumption less than the allowed limit.

Keywords

RTL test scheduling, power consumption, circuit partitioning, testable blocks

Authors

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

RIV year

2008

Released

14. 10. 2008

Publisher

Masaryk University

Location

Znojmo

ISBN

978-80-7355-082-0

Book

4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

265

Pages to

265

Pages count

1

URL

https://www.fit.vut.cz/research/publication/8795/

BibTex

@inproceedings{BUT30718,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Power Conscious RTL Test Scheduling",
  booktitle="4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2008",
  pages="265--265",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-7355-082-0",
  url="https://www.fit.vut.cz/research/publication/8795/"
}