Publication detail

Memory Optimization for Packet Classification Algorithms

KOŘENEK, J. PUŠ, V.

Original Title

Memory Optimization for Packet Classification Algorithms

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

We propose novel method how to reduce data structure size for the family of packet classification algorithms at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the crossproduct nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.

Keywords

Packet Classification, FPGA, SRAM, Optimization

Authors

KOŘENEK, J.; PUŠ, V.

RIV year

2009

Released

19. 9. 2009

Publisher

Association for Computing Machinery

Location

New York

ISBN

978-1-60558-630-4

Book

Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

Edition

Association for Computing Machinery

Pages from

165

Pages to

166

Pages count

2

URL

https://www.fit.vut.cz/research/publication/9113/

BibTex

@inproceedings{BUT30760,
  author="Jan {Kořenek} and Viktor {Puš}",
  title="Memory Optimization for Packet Classification Algorithms",
  booktitle="Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems",
  year="2009",
  series="Association for Computing Machinery",
  pages="165--166",
  publisher="Association for Computing Machinery",
  address="New York",
  isbn="978-1-60558-630-4",
  url="https://www.fit.vut.cz/research/publication/9113/"
}