Publication detail

On Lookup Table Cascade-Based Realizations of Arbiters

MIKUŠEK, P. DVOŘÁK, V.

Original Title

On Lookup Table Cascade-Based Realizations of Arbiters

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

This paper presents a new algorithm of iterative decomposition for multiple-output Boolean functions with an embedded heuristics to order variables. The algorithm produces a cascade of look-up tables (LUTs) that implements the given function and simultaneously a sub-optimal Multi-Terminal Binary Decision Diagram (MTBDD). The LUT cascade can be used for pipelined processing on FPGAs with BRAMs or at a non-traditional synthesis of large combinational and sequential circuits. On the other hand, suboptimal MTBBDs can serve as prototypes for efficient firmware implementation, especially when a micro-programmed controller that firmware runs on supports multi-way branching. A novel technique is illustrated on practical examples of three types of arbiters. It may be quite useful as a more flexible alternative implementation of digital systems with increased testability and improved manufacturability.

Keywords

LUT cascades, Multi-Terminal BDDs, iterative disjunctive decomposition, arbiter circuits

Authors

MIKUŠEK, P.; DVOŘÁK, V.

RIV year

2008

Released

8. 6. 2008

Publisher

IEEE Computer Society

Location

Parma

ISBN

978-0-7695-3277-6

Book

11th EUROMICRO Conference on Digital System Design DSD 2008

Pages from

795

Pages to

802

Pages count

8

URL

https://www.fit.vut.cz/research/publication/8635/

BibTex

@inproceedings{BUT32056,
  author="Petr {Mikušek} and Václav {Dvořák}",
  title="On Lookup Table Cascade-Based Realizations of Arbiters",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  year="2008",
  pages="795--802",
  publisher="IEEE Computer Society",
  address="Parma",
  isbn="978-0-7695-3277-6",
  url="https://www.fit.vut.cz/research/publication/8635/"
}