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STRAKA, M. KAŠTIL, J. KOTÁSEK, Z.
Original Title
Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs
Type
article in a collection out of WoS and Scopus
Language
English
Original Abstract
Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.
Keywords
fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration
Authors
STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.
RIV year
2010
Released
25. 2. 2010
Publisher
IEEE Computer Society
Location
Wien
ISBN
978-1-4244-6610-8
Book
Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
Pages from
173
Pages to
176
Pages count
4
BibTex
@inproceedings{BUT34646, author="Martin {Straka} and Jan {Kaštil} and Zdeněk {Kotásek}", title="Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs", booktitle="Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010", year="2010", pages="173--176", publisher="IEEE Computer Society", address="Wien", isbn="978-1-4244-6610-8" }