Memory Optimization for Packet Classification Algorithms in FPGA

article in a collection out of WoS and Scopus

English

Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.

packet classification, sram, fpga, tcam

KOŘENEK, J.; PUŠ, V.

2010

14. 4. 2010

IEEE Computer Society

Vídeň

978-1-4244-6610-8

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

297

300

4

https://www.fit.vut.cz/research/publication/9198/

paper.pdf