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Publication detail
YOUNES, D. ŠTEFFAN, P.
Original Title
IMPROVED DESIGN FOR MODULO 2n+1 ADDER
Type
conference paper
Language
English
Original Abstract
2n + 1 modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this paper a novel circuit design for 2n + 1 adder has been proposed. This design reduces the bit length of operands used in most 2n + 1 residue adders from (n+1) to n bit long. Thereby complexity of VLSI implementation and delay of the overall system will be reduced. The proposed circuit has been implemented using VHDL to prove the theoretical consideration.
Keywords
Residue Number System, 2n + 1 adder, modular adder, subtractor
Authors
YOUNES, D.; ŠTEFFAN, P.
RIV year
2010
Released
1. 9. 2010
Location
Brno
ISBN
978-80-214-4138-5
Book
Electronic Devices and Systems IMAPS CS International Conference 2010
Pages from
346
Pages to
348
Pages count
3
BibTex
@inproceedings{BUT34792, author="Dina {Younes} and Pavel {Šteffan}", title="IMPROVED DESIGN FOR MODULO 2n+1 ADDER", booktitle="Electronic Devices and Systems IMAPS CS International Conference 2010", year="2010", pages="346--348", address="Brno", isbn="978-80-214-4138-5" }