Publication detail

Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware

DVOŘÁK, V.

Original Title

Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware

Type

journal article - other

Language

English

Original Abstract

The paper addresses software and firmware implementation of multiple-output Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means of compact representation of a large class of sparse Boolean functions, evaluation of which then reduces to multiple indirect memory accesses. The method is compared to a technique of direct PLA emulation and is illustrated on examples. A specialized micro-engine is proposed for even faster evaluation than is possible with universal microprocessors. The presented method is flexible in making trade-offs between performance and memory footprint and may be useful for embedded applications where the processing speed is not critical. Evaluation may run on various CPUs and DSP cores or slightly faster on FPGA-based micro-programmed controllers.

Keywords

Embedded software, Boolean function evaluation, Binary Decision Diagrams, LUT cascades   

Authors

DVOŘÁK, V.

RIV year

2007

Released

29. 8. 2007

ISBN

1796-217X

Periodical

Journal of Software

Year of study

2

Number

5

State

Republic of Finland

Pages from

52

Pages to

63

Pages count

12

URL

https://www.fit.vut.cz/research/publication/8405/

BibTex

@article{BUT45165,
  author="Václav {Dvořák}",
  title="Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware",
  journal="Journal of Software",
  year="2007",
  volume="2",
  number="5",
  pages="52--63",
  issn="1796-217X",
  url="https://www.fit.vut.cz/research/publication/8405/"
}

Documents

JSW62480_new.pdf