Publication detail

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

ŠKARVADA, J. KOTÁSEK, Z. HERRMAN, T.

Original Title

Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties

Type

journal article - other

Language

English

Original Abstract

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

Keywords

Testable block, Circuit partitioning, Test vectors reordering, Scan cells reordering, Low power

Authors

ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T.

RIV year

2008

Released

4. 4. 2008

ISBN

0141-9331

Periodical

Microprocessors and Microsystems

Year of study

32

Number

5

State

Kingdom of the Netherlands

Pages from

296

Pages to

302

Pages count

7

URL

http://dx.doi.org/10.1016/j.micpro.2008.03.002

BibTex

@article{BUT49469,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties",
  journal="Microprocessors and Microsystems",
  year="2008",
  volume="32",
  number="5",
  pages="296--302",
  issn="0141-9331",
  url="http://dx.doi.org/10.1016/j.micpro.2008.03.002"
}