Product detail

Tools for split RTL circuit into Testable blocks

HERRMAN, T. KOTÁSEK, Z.

Product type

software

Abstract

Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog.

Keywords

RTL, testability analysis, formal model, scan chain design, Testable block

Create date

15. 2. 2007

Location

http://www.fit.vutbr.cz/research/prod/index.php?id=57¬itle=1

Possibilities of use

K využití výsledku jiným subjektem je vždy nutné nabytí licence

Licence fee

Poskytovatel licence na výsledek nepožaduje licenční poplatek

www

http://www.fit.vutbr.cz/research/prod/index.php?id=57¬itle=1

Documents

circuits.zip
TB.ZIP