Hybrid dual-mode frequency synthesis for cognitive multi-radio front-ends

Hybrid dual-mode frequency synthesis for cognitive multi-radio front-ends

Peer-reviewed article not indexed in WoS or Scopus

This paper investigates a novel approach to reconfigurable frequency synthesis for flexible radio transceivers in future cognitive multi-radios. The frequency range covered by the proposed multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards operating in the radio band ranging from 800 MHz to 6 GHz. A hybrid Phase Locked Loop (PLL) based frequency synthesizer is proposed here and a novel switching protocol is presented and validated on an experimental evaluation board. The proposed architecture combines fractional-N and integer-N modes of operation along with a switched loop filter topology. Compared to standard PLL techniques, the proposed configuration provides great flexibility options and moreover, it offers relatively low circuit complexity and low power consumption. The proposed architecture provides reconfigurability of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards.

This paper investigates a novel approach to reconfigurable frequency synthesis for flexible radio transceivers in future cognitive multi-radios. The frequency range covered by the proposed multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards operating in the radio band ranging from 800 MHz to 6 GHz. A hybrid Phase Locked Loop (PLL) based frequency synthesizer is proposed here and a novel switching protocol is presented and validated on an experimental evaluation board. The proposed architecture combines fractional-N and integer-N modes of operation along with a switched loop filter topology. Compared to standard PLL techniques, the proposed configuration provides great flexibility options and moreover, it offers relatively low circuit complexity and low power consumption. The proposed architecture provides reconfigurability of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards.

Frequency synthesis, phase locked loop, cognitive radio

Frequency synthesis, phase locked loop, cognitive radio

VALENTA, V.; BAUDOIN, G.; VILLEGAS, M.; MARŠÁLEK, R.

2013

01.05.2012

0929-6212

WIRELESS PERSONAL COMMUNICATIONS

2012 (64)

1

Kingdom of the Netherlands

197

210

15