Publication result detail

VHDL Procedure for Combinational Divider

FEDRA, Z.; KOLOUCH, J.

Original Title

VHDL Procedure for Combinational Divider

English Title

VHDL Procedure for Combinational Divider

Type

Paper in proceedings (conference paper)

Original Abstract

In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.

English abstract

In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables.

Keywords

divider, FPGA, implementation, procedure, static timing analysis, VHDL

Key words in English

divider, FPGA, implementation, procedure, static timing analysis, VHDL

Authors

FEDRA, Z.; KOLOUCH, J.

RIV year

2012

Released

20.08.2011

ISBN

978-1-4577-1761-1

Book

34th International Conference on Telecommunications and Signal Processing, TSP 2011

Pages from

469

Pages to

471

Pages count

3

BibTex

@inproceedings{BUT74709,
  author="Zbyněk {Fedra} and Jaromír {Kolouch}",
  title="VHDL Procedure for Combinational Divider",
  booktitle="34th International Conference on Telecommunications and Signal Processing, TSP 2011",
  year="2011",
  pages="469--471",
  isbn="978-1-4577-1761-1"
}