FPGA-based In-system Jitter Measurement

conference paper

English

The paper presents a simple jitter measurement device implemented in FPGA. The device for the jitter measurement is closely coupled with a blind oversampling data recovery circuit (BO-CDR), which is sometimes used in asynchronous high speed data receivers as an alternative to the traditional PLL-based CDR circuit. The jitter measurement itself is based on estimating the edge density distribution over one unit interval via evaluating the number of detected edges in particular time intervals. The method enables simultaneous data transmission and real-time signal quality estimation without affecting the data signal, which is probably the main benefit of the proposed solution. There is no need for any additional hardware except the FPGA. The jitter evaluation is done completely within the gate array, requiring a few of its hardware resources. The proposed device was successfully implemented and tested on an optical data link. Real measurement results are presented together with reference measurements acquired using an oscilloscope.

bit error rate, confidence level, FPGA, jitter

KUBÍČEK, M.; KOLKA, Z.

2011

23. 11. 2011

Fakulta elektrotechniky, ČVUT

Technická 2, Praha 6, 166 27

978-80-01-04887-0

ISMOT Proceedings 2011

1

1

277

280

4