Publication detail

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

OTERO, A. SALVADOR, R. MORA, J. DE LA TORRE, E. RIESGO, T. SEKANINA, L.

Original Title

A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Modern FPGAs with Dynamic and Partial Reconfiguration (DPR) features allow the implementation of complex, yet flexible, hardware systems. Combining this flexibility with evolvable hardware techniques, real adaptive systems, able to reconfigure themselves according to environmental changes, can be envisaged. In this paper, a highly regular and modular architecture combined with a fast reconfiguration mechanism is proposed, allowing the introduction of dynamic and partial reconfiguration in the evolvable hardware loop. Results and use case show that, following this approach, evolvable processing IP Cores can be built, providing intensive data processing capabilities, improving data and delay overheads with respect to previous proposals. Results also show that, in the worst case (maximum mutation rate), average reconfiguration time is 5 times lower than evaluation time.

Keywords

field programmable gate array, adaptive hardware, dynamic partial reconfiguration, IP core, evolvable hardware

Authors

OTERO, A.; SALVADOR, R.; MORA, J.; DE LA TORRE, E.; RIESGO, T.; SEKANINA, L.

RIV year

2011

Released

15. 6. 2011

Publisher

IEEE Computer Society

Location

Los Alamitos

ISBN

978-1-4577-0599-1

Book

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems

Pages from

336

Pages to

343

Pages count

8

BibTex

@inproceedings{BUT76399,
  author="Andres {Otero} and Ruben {Salvador} and Javier {Mora} and Eduardo {De la Torre} and Teresa {Riesgo} and Lukáš {Sekanina}",
  title="A Fast Reconfigurable 2D HW Core Architecture on FPGAs for Evolvable Self-Adaptive Systems",
  booktitle="Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems",
  year="2011",
  pages="336--343",
  publisher="IEEE Computer Society",
  address="Los Alamitos",
  isbn="978-1-4577-0599-1"
}