Publication detail

1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA

ŠTOHANZL, M. FEDRA, Z. BOBULA, M.

Original Title

1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA

Type

conference paper

Language

English

Original Abstract

This paper presents a study about the hardware implementation of the TCP/IP and UDP/IP headers compression for the point-to-point communication. The implementation is focused on the achievement of minimum latency and high compression ratio. The applied compression technique is a dictionary-based method. For the TCP/IP, the fixed length of the compressed header was implemented. On the contrary, the variable length of the compressed header was implemented for the UDP/IP. The dictionaries are filled from the original data on both sides. No additional transmissions are used for retaining the continuity of the dictionary content.

Keywords

Field Programable Gate Array (FPGA), Ethernet, header, compression, connection, IP, TCP, UDP

Authors

ŠTOHANZL, M.; FEDRA, Z.; BOBULA, M.

RIV year

2012

Released

19. 11. 2012

ISBN

978-1-61208-231-8

Book

Proceedings of The Seventh International Conference on Systems and Networks Communications, ICSNC 2012

Pages from

136

Pages to

142

Pages count

7

BibTex

@inproceedings{BUT94971,
  author="Milan {Štohanzl} and Zbyněk {Fedra} and Marek {Bobula}",
  title="1 Gbps Ethernet TCP/IP and UDP/IP Header Compression in FPGA",
  booktitle="Proceedings of The Seventh International Conference on Systems and Networks Communications, ICSNC 2012",
  year="2012",
  pages="136--142",
  isbn="978-1-61208-231-8"
}