Terrain Rendering Algorithm Performance Analysis

article in a collection out of WoS and Scopus

English

Nowadays, the flight guidance equipment supplies practically all the information, required for aircraft navigation. Pseudo-realistic terrain visualization is undoubtedly an important part of this information. Although modern graphics processors are able to render realistic terrain at interactive frame rates, in some applications, it is beneficial to use low-power graphics hardware, perhaps from weight or power supply capacity restrictions. These low-power graphics processors typically manifest much lower computational power than conventional hardware, severely limiting the capability of terrain visualization. A novel method for caching terrain tiles is presented in this paper, enabling faster and more detailed terrain rendering, using lighter devices that consume less power. The main focus was on memory and time efficiency on common low-power graphics hardware. The terrain rendering algorithm being employed in our implementation is derived from the seamless patches algorithm. Different aspects of terrain tile swapping were examined in order to devise a simple hardware metric. An efficient tile caching approach was developed, based on this hardware metric, and its performance was evaluated.

terrain rendering, tile caching, allocation algorithm, complexity

POLOK, L.; BARTOŇ, R.; CHUDÝ, P.; KRŠEK, P.; SMRŽ, P.; DITTRICH, P.

2012

14. 10. 2012

IEEE Computer Society

Williamsburg, VA, USA

978-1-4673-1699-6

Proceedings of the 31st Digital Avionics Systems Conference

1

7

7

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6382297

191polok.pdf