Publication detail

An Abstraction of Multi-Port Memories with Arbitrary Addressable Units

CHARVÁT, L. SMRČKA, A. VOJNAR, T.

Original Title

An Abstraction of Multi-Port Memories with Arbitrary Addressable Units

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper describes a technique for automatic generation of abstract models of memories that can be used for efficient formal verification of hardware designs. Our approach is able to handle addressing of different sizes of data, such as quad words, double words, words, or bytes, at the same time. The technique is also applicable for memories with multiple read and write ports, memories with read and write operations with zero- or single-clock delay, and it allows the memory to start with a random initial state allowing one to formally verify the given design for all initial contents of the memory. Our abstraction allows large register-files and memories to be represented in a way that dramatically reduces the state space to be explored during formal verification of microprocessor designs.

Keywords

memory, register file, automatic formal verification, model checking

Authors

CHARVÁT, L.; SMRČKA, A.; VOJNAR, T.

RIV year

2013

Released

15. 5. 2013

Publisher

Springer Verlag

Location

Berlin Heidelberg

ISBN

978-3-642-53855-1

Book

Computer Aided Systems Theory - EUROCAST 2013

Edition

Lecture Notes in Computer Science

Pages from

460

Pages to

468

Pages count

8

BibTex

@inproceedings{BUT103508,
  author="Lukáš {Charvát} and Aleš {Smrčka} and Tomáš {Vojnar}",
  title="An Abstraction of Multi-Port Memories with Arbitrary Addressable Units",
  booktitle="Computer Aided Systems Theory - EUROCAST 2013",
  year="2013",
  series="Lecture Notes in Computer Science",
  volume="8111",
  pages="460--468",
  publisher="Springer Verlag",
  address="Berlin Heidelberg",
  isbn="978-3-642-53855-1"
}