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VAŠÍČEK, Z.
Original Title
Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates
Type
conference paper
Language
English
Original Abstract
A new approach to the evolutionary optimization of large digital circuits is introduced in this paper. In contrast with evolutionary circuit design, the goal of the evolutionary circuit optimization is to minimize the number of gates (or other non-functional parameters) of already functional circuit. The method combines a circuit simulation with a formal verification in order to detect the functional inequivalence of the parent and its offspring. An extensive set of 100 benchmarks circuits is used to evaluate the performance of the method as well as the utilized evolutionary approach. Moreover, the role of neutral mutations in the context of evolutionary optimization is investigated. In average, the method enabled a 34% reduction in gate count even if the optimizer was executed only for 15 minutes.
Keywords
Genetic programming, Cartesian Genetic Programming, Evolutionary optimization, Combinational circuits, Formal verification
Authors
RIV year
2015
Released
15. 3. 2015
Publisher
Springer International Publishing
Location
Berlin
ISBN
978-3-319-16500-4
Book
Genetic Programming, 18th European Conference, EuroGP 2015
Edition
LCNS 9025
Pages from
139
Pages to
150
Pages count
12
URL
https://www.fit.vut.cz/research/publication/10773/
BibTex
@inproceedings{BUT119799, author="Zdeněk {Vašíček}", title="Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates", booktitle="Genetic Programming, 18th European Conference, EuroGP 2015", year="2015", series="LCNS 9025", pages="139--150", publisher="Springer International Publishing", address="Berlin", doi="10.1007/978-3-319-16501-1\{_}12", isbn="978-3-319-16500-4", url="https://www.fit.vut.cz/research/publication/10773/" }