Přístupnostní navigace
E-application
Search Search Close
Publication detail
SÁNCHEZ-CLEMENTE, A. ENTRENA, L. HRBÁČEK, R. SEKANINA, L.
Original Title
Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches
Type
journal article in Web of Science
Language
English
Original Abstract
Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.
Keywords
Approximate logic circuit, error mitigation, evolutionary computing, single-event transient (SET), single-event upset (SEU)
Authors
SÁNCHEZ-CLEMENTE, A.; ENTRENA, L.; HRBÁČEK, R.; SEKANINA, L.
Released
1. 12. 2016
ISBN
0018-9529
Periodical
IEEE TRANSACTIONS ON RELIABILITY
Year of study
65
Number
4
State
United States of America
Pages from
1871
Pages to
1883
Pages count
13
URL
http://dx.doi.org/10.1109/TR.2016.2604918
BibTex
@article{BUT130920, author="Antonio José {Sánchez-Clemente} and Luis {Entrena} and Radek {Hrbáček} and Lukáš {Sekanina}", title="Error Mitigation using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches", journal="IEEE TRANSACTIONS ON RELIABILITY", year="2016", volume="65", number="4", pages="1871--1883", doi="10.1109/TR.2016.2604918", issn="0018-9529", url="http://dx.doi.org/10.1109/TR.2016.2604918" }