High-speed Regular Expression Matching with Pipelined Automata

conference paper

English

Pattern matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links, pattern matching architectures have to be improved in order to retain wire-speed processing. Multi-striding is a well-known technique on how to increase throughput of pattern matching architectures. In the paper we provide an analysis of scalability of multi-striding and show that it does not scale well and cannot be used for 100Gbps throughput because utilization of FPGA resources grows exponentially. Therefore, we have designed a new hardware architecture for high-speed pattern matching that combines the multi-striding technique and parallel processing using pipelined finite state machines (FSMs). The architecture shares a single packet buffer for all parallel FSMs. Efficient implementation of the packet buffer reduces the number of BlockRAMs to 18% when compared to simple parallel implementation. Instead of multiplexing input data, the architecture pipelines the states of FSMs. Such pipelined processing with only local communication has a direct positive impact on frequency and throughput and allows us to scale the architecture to hundreds of Gbps.

FPGA, NFA, multi-striding, pattern matching, regular expressions, finite automata, pipelined automata, high-speed networks, 100Gbps, 40Gbps, 10Gbps, 100G Ethernet, 40G Ethernet, 10G Ethernet

MATOUŠEK, D.; KOŘENEK, J.; PUŠ, V.

7. 12. 2016

IEEE Computer Society

Xi'an

978-1-5090-5602-6

Proceedings of the 2016 International Conference on Field Programmable Technology

93

100

8

http://ieeexplore.ieee.org/document/7929431/