Efficient Implementation of Bi-functional RTL Components - Case Study

conference paper

English

The emergence of highly optimized implementations of many bi-functional gates allows an efficient implementation of components at a higher level of abstraction. In several classes of applications which typically involve RT level oriented design approach, these components can circumvent various issues related to synthesis of multifunctional circuits at the gate level. While the synthesis at the gate level is difficult, at RT level a skilled designer is still able to design a far more complex circuits by himself. If a set of efficient bi-functional RTL components is available, their utilization is expected to improve efficiency of the resulting circuit. In this paper, validity of this assumption is demonstrated through a design of bi-functional adder/subtractor circuit. At the gate level, one-bit full adder/subtractor circuit was created and optimised. This circuit was subsequently utilised for design of multi-bit adder/subtractor which was successfully simulated at the transistor level with MOSFET implementation of bi-functional logic gates. Besides adder/subtractor, an increment/decrement RTL component is also presented.

Multifunctional electronics, bi-functional RTL component, bi-functional gate, full adder/subtractor, half adder/subtractor, increment/decrement.

NEVORAL, J.; RŮŽIČKA, R.

20. 11. 2018

IEEE Circuits and Systems Society

Valletta

978-1-5386-7680-6

2018 New Generation of CAS (NGCAS)

25

28

4