Publication detail

A Tool for VLIW Processors Code Optimizing

MEGO, R. FRÝZA, T.

Original Title

A Tool for VLIW Processors Code Optimizing

Type

conference paper

Language

English

Original Abstract

The paper demonstrates the behavior of low- and high-level programming languages on the multicore digital signal processors based on Very Long Instruction Word architecture. The aim of the paper is to present a tool that can be used to implement any digital signal processing algorithm on such processors with efficiency of the low-level languages, but with the advantages of the high-level programming languages. Preliminary result is the software that uses a signal-flow graph approach to describe an algorithm, generates low-level assembly code and provides (graphical) information about the algorithm.

Keywords

VLIW, low-level, assembly, C6678, FFT, DCT

Authors

MEGO, R.; FRÝZA, T.

Released

15. 2. 2019

Publisher

Ain Shams University

Location

Cairo, Egypt

ISBN

978-1-5386-5111-7

Book

Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)

Pages from

601

Pages to

604

Pages count

4

URL

https://ieeexplore.ieee.org/document/8639186

BibTex

@inproceedings{BUT155771,
  author="Roman {Mego} and Tomáš {Frýza}",
  title="A Tool for VLIW Processors Code Optimizing",
  booktitle="Proceedings of the 13th International Conference on Computer Engineering and Systems (ICCES 2018)",
  year="2019",
  pages="601--604",
  publisher="Ain Shams University",
  address="Cairo, Egypt",
  doi="10.1109/ICCES.2018.8639186",
  isbn="978-1-5386-5111-7",
  url="https://ieeexplore.ieee.org/document/8639186"
}