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PRÁŠEK, J. HOUŠKA, D. HRDÝ, R. HUBÁLEK, J. SCHMID, U.
Original Title
Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage
Type
conference paper
Language
English
Original Abstract
In this paper we optimize cryogenic deep reactive ion etching processes to achieve the best aspect ratios of holes in a silicon substrate that is supposed to be used for fabrication of on-chip energy storage. By optimizing capacitively coupled plasma source power and oxygen flow, aspect ratio of 28:1 for holes of 2 µm in diameter was achieved. Bottling effect was suppressed by tuning capacitively coupled plasma, inductively coupled plasma sources and process pressure at the same time. The smoothness and purity of the hole walls are other parameters we investigate using atomic force microscopy and X-ray photoelectron spectroscopy.
Keywords
dry etching; DRIE; cryogenic process; Bosch process; energy storage
Authors
PRÁŠEK, J.; HOUŠKA, D.; HRDÝ, R.; HUBÁLEK, J.; SCHMID, U.
Released
26. 8. 2019
Publisher
IEEE Computer Society
Location
Poland
ISBN
978-1-7281-1874-1
Book
42st International Spring Seminar on Electronics Technology ISSE2019
2161-2536
Periodical
International Spring Seminar on Electronics Technology ISSE
Year of study
2019
State
United States of America
Pages from
1
Pages to
6
Pages count
URL
https://ieeexplore.ieee.org/abstract/document/8810293
BibTex
@inproceedings{BUT161135, author="Jan {Prášek} and David {Houška} and Radim {Hrdý} and Jaromír {Hubálek} and Ulrich {Schmid}", title="Optimization of Cryogenic Deep Reactive Ion Etching Process for On-Chip Energy Storage ", booktitle="42st International Spring Seminar on Electronics Technology ISSE2019", year="2019", journal="International Spring Seminar on Electronics Technology ISSE", volume="2019", pages="1--6", publisher="IEEE Computer Society", address="Poland", doi="10.1109/ISSE.2019.8810293", isbn="978-1-7281-1874-1", issn="2161-2536", url="https://ieeexplore.ieee.org/abstract/document/8810293" }