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CABAL, J. BENÁČEK, P. FOLTOVÁ, J. HOLUB, J.
Original Title
Scalable P4 Deparser for Speeds Over 100 Gbps
Type
abstract
Language
English
Original Abstract
The P4 language is a language suitable for the description of packet processing inside a network device. The typical P4 device consists of three main building blocks: Parser, Match+Action Tables and Deparser. The deparsing is the most challenging block because the main task of this block is to assemble the output packet based on changes in Match+Action Tables. This operation can be quite complicated in the case of high-speed networks. In this work, we present the scalable architecture (in term of the throughput) of a deparsing circuit which is suitable for implementation in FPGAs.
Keywords
field programmable gate arrays (FPGA), high speed networks, 100gbps, building blockes, deparser, network devices, P4 language, packet processing, packet-based, scalable architectures, computers
Authors
CABAL, J.; BENÁČEK, P.; FOLTOVÁ, J.; HOLUB, J.
Released
28. 4. 2019
Location
Los Alamitos
ISBN
978-1-7281-1131-5
Book
Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Pages from
323
Pages to
Pages count
1
URL
https://ieeexplore.ieee.org/document/8735524
BibTex
@misc{BUT163388, author="Jakub {Cabal} and Pavel {Benáček} and Jana {Foltová} and Juraj {Holub}", title="Scalable P4 Deparser for Speeds Over 100 Gbps", booktitle="Annual IEEE Symposium on Field-Programmable Custom Computing Machines", year="2019", pages="323--323", address="Los Alamitos", doi="10.1109/FCCM.2019.00064", isbn="978-1-7281-1131-5", url="https://ieeexplore.ieee.org/document/8735524", note="abstract" }