Publication detail

Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

ŠOTNER, R. JEŘÁBEK, J. POLÁK, L. PETRŽELA, J.

Original Title

Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

Type

journal article in Web of Science

Language

English

Original Abstract

This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.

Keywords

Capacitance; Resistance; Capacitors; Topology; Tuning; Impedance; Attenuation; Adjustability; capacitance multiplication; current conveyor; current gain; differential voltage buffer; electronic tuning; multiplication factor adjustment; voltage gain

Authors

ŠOTNER, R.; JEŘÁBEK, J.; POLÁK, L.; PETRŽELA, J.

Released

5. 8. 2020

Publisher

IEEE

Location

PISCATAWAY

ISBN

2169-3536

Periodical

IEEE Access

Year of study

8

Number

1

State

United States of America

Pages from

144382

Pages to

144392

Pages count

11

URL

https://ieeexplore.ieee.org/document/9159558

Full text in the Digital Library

http://hdl.handle.net/11012/195248

BibTex

@article{BUT165021,
  author="Roman {Šotner} and Jan {Jeřábek} and Ladislav {Polák} and Jiří {Petržela}",
  title="Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique",
  journal="IEEE Access",
  year="2020",
  volume="8",
  number="1",
  pages="144382--144392",
  doi="10.1109/ACCESS.2020.3014388",
  issn="2169-3536",
  url="https://ieeexplore.ieee.org/document/9159558"
}