Publication detail

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

LOJDA, J. PÁNEK, R. PODIVÍNSKÝ, J. ČEKAN, O. KRČMA, M. KOTÁSEK, Z.

Original Title

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Type

conference paper

Language

English

Original Abstract

In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.

Keywords

Electronic Lock, Stepper Motor, Fault Tolerance, Fault Injection, FPGA, IMEM, DMEM, LUT

Authors

LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z.

Released

1. 8. 2020

Publisher

Institute of Electrical and Electronics Engineers

Location

Kranj

ISBN

978-1-7281-9535-3

Book

Proceedings - Euromicro Conference on Digital System Design, DSD 2020

Pages from

680

Pages to

683

Pages count

4

URL

https://www.fit.vut.cz/research/publication/12256/

BibTex

@inproceedings{BUT168127,
  author="Jakub {Lojda} and Richard {Pánek} and Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Zdeněk {Kotásek}",
  title="Hardening of Smart Electronic Lock Software against Random and Deliberate Faults",
  booktitle="Proceedings - Euromicro Conference on Digital System Design, DSD 2020",
  year="2020",
  pages="680--683",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Kranj",
  doi="10.1109/DSD51259.2020.00110",
  isbn="978-1-7281-9535-3",
  url="https://www.fit.vut.cz/research/publication/12256/"
}

Documents

DSD_2020_Lojda_et_al.pdf