Publication detail

Optimization of BDD-based Approximation Error Metrics Calculations

MRÁZEK, V.

Original Title

Optimization of BDD-based Approximation Error Metrics Calculations

Type

conference paper

Language

English

Original Abstract

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.

Keywords

approximate computing, error evaluation, relaxed equivalence checking

Authors

MRÁZEK, V.

Released

8. 7. 2022

Publisher

Institute of Electrical and Electronics Engineers

Location

Paphos

ISBN

978-1-6654-6605-9

Book

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)

Pages from

86

Pages to

91

Pages count

6

BibTex

@inproceedings{BUT177787,
  author="Vojtěch {Mrázek}",
  title="Optimization of BDD-based Approximation Error Metrics Calculations",
  booktitle="IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)",
  year="2022",
  pages="86--91",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Paphos",
  doi="10.1109/ISVLSI54635.2022.00028",
  isbn="978-1-6654-6605-9"
}