Publication detail

On the Petri Net Based Test Scheduling

RŮŽIČKA, R.

Original Title

On the Petri Net Based Test Scheduling

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

This paper discusses some problems with test scheduling optimization of register transfer level (RTL) digital circuit design. The Petri net model, previously proposed for testability verification purposes is now used as a base of C/E system which models test application process. To schedule application of test patterns to elements of a circuit under test, possibility of concurrency must be considered firstly. Parallelism during test application process can significantly reduce time of testing. Another advantage of the approach is that all methods are described formally and are proved.

Keywords

RTL digital circuit testability, test scheduling optimization

Authors

RŮŽIČKA, R.

RIV year

2005

Released

30. 8. 2005

Publisher

Johannes Kepler University Linz

Location

Linz

ISBN

3-902457-09-0

Book

Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005

Pages from

18

Pages to

19

Pages count

2

BibTex

@inproceedings{BUT18034,
  author="Richard {Růžička}",
  title="On the Petri Net Based Test Scheduling",
  booktitle="Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005",
  year="2005",
  pages="18--19",
  publisher="Johannes Kepler University Linz",
  address="Linz",
  isbn="3-902457-09-0"
}