Publication detail

On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits

STRNADEL, J., PEČENKA, T., SEKANINA, L.

Original Title

On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits

Type

conference paper

Language

English

Original Abstract

Use of benchmark designs has become an important part of a process of designing complex systems. However, existing register-transfer level benchmark suites are not sufficient for evaluation of new architectures and tools; synthetic benchmark circuits are an alternative. In the paper, it is demonstrated how evolutionary techniques can be used to generate synthetic benchmarks covering a wide scale of testability properties. The generation process is driven by a register-transfer level testability analysis method and generated benchmarks are stored in synthesizable VHDL source-code. Results gained by proposed method together with future research trends are discussed at the end of the paper.

Keywords

Register-transfer level, synthetic benchmark circuit, testability analysis, evolutionary algorithm

 

Authors

STRNADEL, J., PEČENKA, T., SEKANINA, L.

RIV year

2005

Released

8. 9. 2005

Publisher

Slovak University of Technology in Bratislava

Location

Bratislava

Pages from

107

Pages to

110

Pages count

4

BibTex

@inproceedings{BUT18046,
  author="Josef {Strnadel} and Tomáš {Pečenka} and Lukáš {Sekanina}",
  title="On Testability Analysis Driven Generation of Synthetic Register-Transfer Level Benchmark Circuits",
  booktitle="Proceedings of 5th Electronic Circuits and Systems Conference",
  year="2005",
  pages="107--110",
  publisher="Slovak University of Technology in Bratislava",
  address="Bratislava"
}