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MEGO, R. FRÝZA, T.
Original Title
Instruction mapping techniques for processors with very long instruction word architectures
Type
journal article in Web of Science
Language
English
Original Abstract
This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.
Keywords
digital signal processors, parallel architectures, low-level code, instruction mapping, signal-flow graph
Authors
MEGO, R.; FRÝZA, T.
Released
12. 12. 2022
Publisher
FEI STU Bratislava
Location
Bratislava
ISBN
1339-309X
Periodical
Journal of Electrical Engineering
Year of study
73
Number
6
State
Slovak Republic
Pages from
387
Pages to
395
Pages count
9
URL
http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf
BibTex
@article{BUT180540, author="Roman {Mego} and Tomáš {Frýza}", title="Instruction mapping techniques for processors with very long instruction word architectures", journal="Journal of Electrical Engineering", year="2022", volume="73", number="6", pages="387--395", doi="10.2478/jee-2022-0053", issn="1339-309X", url="http://iris.elf.stuba.sk/JEEEC/data/pdf/6_122-03.pdf" }