Publication detail

RT Level Testability Analysis In PROLOG Enviroment

KOTÁSEK, Z. ZBOŘIL, F.

Original Title

RT Level Testability Analysis In PROLOG Enviroment

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Keywords

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Authors

KOTÁSEK, Z.; ZBOŘIL, F.

Released

1. 1. 1997

Location

Ostrava

ISBN

80-85988-19-4

Book

Proceedings of the DDECS'97

Pages from

47

Pages to

52

Pages count

6

BibTex

@inproceedings{BUT191448,
  author="Zdeněk {Kotásek} and František {Zbořil}",
  title="RT Level Testability Analysis In  PROLOG Enviroment",
  booktitle="Proceedings of the  DDECS'97",
  year="1997",
  pages="47--52",
  address="Ostrava",
  isbn="80-85988-19-4"
}