Publication detail

Formal Approach to RTL Testability Analysis

KOTÁSEK, Z. RŮŽIČKA, R. HLAVIČKA, J.

Original Title

Formal Approach to RTL Testability Analysis

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper a formal approach to the RT level testability analysis is presented. It is based on the structural analysis of the circuit under design and the classification of circuit elements. The elements are classified on the basis of their possible role during the test application. The principles known from the theory of sets and mathematical logic are utilised to define the role of registers during the test application. The principles of developing the RT level testability analysis algorithms are then presented to identify registers for partial scan and parallel paths to apply the test of the circuit.

Keywords

RTL testability analysis

Authors

KOTÁSEK, Z.; RŮŽIČKA, R.; HLAVIČKA, J.

Released

1. 1. 2000

Publisher

unknown

Location

Rio de Janeiro

Pages from

98

Pages to

103

Pages count

6

BibTex

@inproceedings{BUT191916,
  author="Zdeněk {Kotásek} and Richard {Růžička} and Jan {Hlavička}",
  title="Formal Approach to RTL Testability Analysis",
  booktitle="sborník konference IEEE LATW 2000",
  year="2000",
  pages="98--103",
  publisher="unknown",
  address="Rio de Janeiro"
}