Publication detail

CSP-based Modeling of SM Architectures

ČEJKA, R. DVOŘÁK, V.

Original Title

CSP-based Modeling of SM Architectures

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The possibility of modeling of shared memory (SM) architectures using communicating sequential processes (CSP) is described. The CSP-based Transim tool enabled us to perform fair performance comparison of theoretical PRAM model and the message passing (MP) model on one hand and the real bus based SM systems with coherent caches on the other. Various memory update strategies, cache coherence protocols and bus arbitration strategies have been examined, such as write through/write back memory update, write invalidate/write update cache coherence protocols, and the most frequently used bus arbitration strategies (fair, priority-based, random). For comparison we have chosen parallel solution of a large system of linear equations. Performance results are presented and discussed.

Keywords

Shared memory, CSP, Transim, performance comparison

Authors

ČEJKA, R.; DVOŘÁK, V.

Released

1. 1. 1999

Publisher

Faculty of Electrical Engineering and Informatics, University of Technology Košice

Location

Kosice - Herlany

ISBN

80-88922-05-4

Book

Proceedings of conference Computer Engineering and Informatics CE&I'99

Pages from

163

Pages to

168

Pages count

6

BibTex

@inproceedings{BUT192268,
  author="Rudolf {Čejka} and Václav {Dvořák}",
  title="CSP-based Modeling of SM Architectures",
  booktitle="Proceedings of conference Computer Engineering and Informatics CE&I'99",
  year="1999",
  pages="163--168",
  publisher="Faculty of Electrical Engineering and Informatics, University of Technology Košice",
  address="Kosice - Herlany",
  isbn="80-88922-05-4"
}