Publication detail

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J.

Original Title

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

Type

conference paper

Language

English

Original Abstract

The paper describes the utilization of evolutionary algorithms for automatic discovery of benchmark circuits. The main objective of the paper is to show that relatively large and complex (benchmark) circuits can be evolved in case that only a given property (e.g. testability) is required and the function of the circuit is not considered. This principle is demonstrated on automatic discovery of benchmark circuits with predefined structural and diagnostic properties. Fitness evaluation for the proposed algorithm is based on testability analysis with linear time complexity. During the evolution, the solutions which are refused to be synthesized by a design system are excluded from the process of developing a new generation of benchmark circuits. The evolved circuits contain thousands of components and satisfy the required testability properties.

Keywords

evolutionary design, digital circuit, testability analysis, VHDL

Authors

PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J.

RIV year

2005

Released

8. 7. 2005

Publisher

IEEE Computer Society Press

Location

Los Alamitos

ISBN

0-7695-2399-4

Book

Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware

Pages from

51

Pages to

58

Pages count

8

URL

BibTex

@inproceedings{BUT21515,
  author="Tomáš {Pečenka} and Zdeněk {Kotásek} and Lukáš {Sekanina} and Josef {Strnadel}",
  title="Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties",
  booktitle="Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware",
  year="2005",
  pages="51--58",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos",
  isbn="0-7695-2399-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/eh05/eh05bench.pdf"
}