Publication detail

DFT Flow for RT Level Digital Circuits Using iFCoRT System

RŮŽIČKA, R.

Original Title

DFT Flow for RT Level Digital Circuits Using iFCoRT System

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

Our team performs some research activities at the field of testability in past years. These activities results in testability analysis, testability verification, test scheduling and test controller synthesis methodologies. All methodologies are described formally using language of mathematics and theoretical computer science and are based on a formal model of the RT level digital circuit. These tasks can be performed by the iFCoRT system (I path Based, Formally Described and Proved Concept of RTL Digital Circuits Testability). This paper describes how the system can be used during design-for-testability process - a design flow of a testable RT level digital circuit.

Keywords

Testability Analysis, Testability Verification, Design-for-Testability

Authors

RŮŽIČKA, R.

RIV year

2006

Released

20. 9. 2006

Location

Košice

ISBN

80-8073-598-0

Book

Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006

Pages from

292

Pages to

297

Pages count

6

BibTex

@inproceedings{BUT22270,
  author="Richard {Růžička}",
  title="DFT Flow for RT Level Digital Circuits Using iFCoRT System",
  booktitle="Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006",
  year="2006",
  pages="292--297",
  address="Košice",
  isbn="80-8073-598-0"
}