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KUBÍČEK, M.
Original Title
Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals
Type
conference paper
Language
English
Original Abstract
The paper describes VHDL-AMS simulation model of a digital link (with a signal source) together with "software" clock and data recovery module [1] and common recovery circuit incorporating a PLL. Performance of both methods is compared and discussed. Models were created to help to improve the software recovery method. All simulations were performed in the Mentor Graphic's SystemVision 4.4 environment using VHDL-AMS [2] models of signal source, data path and recovery circuits. The soft-ware recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design.
Keywords
Simulation, VHDL-AMS, Clock and data recovery, SystemVision
Authors
RIV year
2007
Released
1. 1. 2007
Publisher
Ing. Zdeněk Novotný CSc., Ondráčková 105, Brno
Location
Vysoké učení technické v Brně
ISBN
978-80-214-3410-3
Book
Proceedings of the 13th Conference Student EEICT 2007
Pages from
266
Pages to
270
Pages count
5
BibTex
@inproceedings{BUT22611, author="Michal {Kubíček}", title="Simulation model of Digital Clock and Data Recovery for Strongly Disturbed Signals", booktitle="Proceedings of the 13th Conference Student EEICT 2007", year="2007", pages="266--270", publisher="Ing. Zdeněk Novotný CSc., Ondráčková 105, Brno", address="Vysoké učení technické v Brně", isbn="978-80-214-3410-3" }