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GAJDA, Z. SEKANINA, L.
Original Title
Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming
Type
article in a collection out of WoS and Scopus
Language
English
Original Abstract
Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.
Keywords
polymorphic circuit, circuit synthesis, evolutionary design, cartesian genetic programming
Authors
GAJDA, Z.; SEKANINA, L.
RIV year
2009
Released
26. 5. 2009
Publisher
IEEE Computational Intelligence Society
Location
NA
ISBN
978-1-4244-2958-5
Book
Proc. of 2009 IEEE Congress on Evolutionary Computation
Pages from
1599
Pages to
1604
Pages count
6
URL
https://www.fit.vut.cz/research/publication/8949/
BibTex
@inproceedings{BUT33725, author="Zbyšek {Gajda} and Lukáš {Sekanina}", title="Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming", booktitle="Proc. of 2009 IEEE Congress on Evolutionary Computation", year="2009", pages="1599--1604", publisher="IEEE Computational Intelligence Society", address="NA", isbn="978-1-4244-2958-5", url="https://www.fit.vut.cz/research/publication/8949/" }