Publication detail

Efficient Hardware Accelerator for Symbolic Regression Problems

VAŠÍČEK, Z. SEKANINA, L.

Original Title

Efficient Hardware Accelerator for Symbolic Regression Problems

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In this paper, a new hardware architecture for the acceleration of symbolic regression problems using Cartesian Genetic Programming (CGP) is presented. In order to minimize the number of expensive memory accesses, a new algorithm is proposed. The search algorithm is implemented using PowerPC processor which is available in Xilinx FPGAs of Virtex family. A significant speedup of evolution is obtained in comparison with a highly optimized software implementation of CGP.

Keywords

hardware acceleration, regression problem, evolutionary design, image filter, fpga, powerpc

Authors

VAŠÍČEK, Z.; SEKANINA, L.

RIV year

2009

Released

13. 11. 2009

Publisher

Masaryk University

Location

Znojmo

ISBN

978-80-87342-04-6

Book

5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

192

Pages to

199

Pages count

8

URL

https://www.fit.vut.cz/research/publication/9108/

BibTex

@inproceedings{BUT34289,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Efficient Hardware Accelerator for Symbolic Regression Problems",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2009",
  pages="192--199",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-87342-04-6",
  url="https://www.fit.vut.cz/research/publication/9108/"
}

Documents

paper.pdf