Publication detail

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

VAŠÍČEK, Z. SEKANINA, L.

Original Title

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

Type

journal article in Scopus

Language

English

Original Abstract

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.  

Keywords

image filter, evolvable hardware, FPGA

Authors

VAŠÍČEK, Z.; SEKANINA, L.

RIV year

2007

Released

19. 4. 2007

ISBN

1751-648X

Periodical

International Journal of Innovative Computing and Applications

Year of study

1

Number

1

State

Swiss Confederation

Pages from

63

Pages to

73

Pages count

11

URL

http://dx.doi.org/10.1504/IJICA.2007.013402

BibTex

@article{BUT45160,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="An Evolvable Hardware System in Xilinx Virtex II Pro FPGA",
  journal="International Journal of Innovative Computing and Applications",
  year="2007",
  volume="1",
  number="1",
  pages="63--73",
  doi="10.1504/IJICA.2007.013402",
  issn="1751-648X",
  url="http://dx.doi.org/10.1504/IJICA.2007.013402"
}