Publication detail

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

VAŠÍČEK, Z. SEKANINA, L.

Original Title

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

Type

journal article - other

Language

English

Original Abstract

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.

Keywords

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

Authors

VAŠÍČEK, Z.; SEKANINA, L.

RIV year

2010

Released

31. 12. 2010

ISBN

1335-9150

Periodical

Computing and Informatics

Year of study

29

Number

6

State

Slovak Republic

Pages from

1359

Pages to

1371

Pages count

13

URL

https://www.fit.vut.cz/research/publication/9421/

BibTex

@article{BUT50732,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units",
  journal="Computing and Informatics",
  year="2010",
  volume="29",
  number="6",
  pages="1359--1371",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/9421/"
}

Documents

11080.pdf