A Programmable Interconnection Network for Multiple Communication Patterns

article in a collection out of WoS and Scopus

English

Application-specific or embedded systems with less than 16 processing cores are too small to use some kind of network on chip (NoC) for interconnection. On the other hand, a crossbar and related circuitry (arbiters, memory elements) are too expensive in terms of chip area. As only few pair-wise and collective communication patterns are mostly used in specific applications, we explore an interconnection network that can support only selected communication patterns and no others. The main contribution of the paper is designing of such networks without routers or arbiters, in a form of programmable combinational logic, with limited crossbar functionality. The interconnection network can be implemented by multiplexers or block RAMs on the FPGA chip at a very low cost. A functional decomposition of the related multiple-output Boolean function into a cascade of block RAM devices is aided by multi-terminal binary decision diagrams and is illustrated on examples.

multiprocessor SoCs; programmable interconnection; on-chip interconnects; crossbar switch; logic decomposition; multi-terminal BDDs

DVOŘÁK, V.; JAROŠ, J.

2011

23. 1. 2011

International Academy, Research, and Industry Association

St. Maarten

978-1-61208-002-4

Proceedings of the Sixth International Conference on Systems, ICONS 2011

6

11

6

https://www.fit.vut.cz/research/publication/9476/