Publication detail

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

VAŠÍČEK, Z. SEKANINA, L.

Original Title

On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming

Type

conference paper

Language

English

Original Abstract

The paper deals with the evolutionary post synthesis optimization of complex combinational circuits with the aim of reducing the area on a chip as much as possible. In order to optimize complex circuits, Cartesian Genetic Programming (CGP) is employed where the fitness function is based on a formal equivalence checking algorithm rather than evaluating all possible input assignments. The standard selection strategy of CGP is modified to be more explorative and so agile in very rugged fitness landscapes. It was shown on the LGSynth93 benchmark circuits that the modified selection strategy leads to more compact circuits in roughly 50% cases. The average area improvement is 24% with respect to the results of conventional synthesis. Delay of optimized circuits was also analyzed. 

Keywords

logic synthesis, optimization, genetic programming, selection

Authors

VAŠÍČEK, Z.; SEKANINA, L.

RIV year

2012

Released

10. 6. 2012

Publisher

Institute of Electrical and Electronics Engineers

Location

CA

ISBN

978-1-4673-1508-1

Book

2012 IEEE World Congress on Computational Intelligence

Pages from

2379

Pages to

2386

Pages count

6

URL

https://www.fit.vut.cz/research/publication/9866/

BibTex

@inproceedings{BUT96926,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="On Area Minimization of Complex Combinational Circuits Using Cartesian Genetic Programming",
  booktitle="2012 IEEE World Congress on Computational Intelligence",
  year="2012",
  pages="2379--2386",
  publisher="Institute of Electrical and Electronics Engineers",
  address="CA",
  doi="10.1109/CEC.2012.6256649",
  isbn="978-1-4673-1508-1",
  url="https://www.fit.vut.cz/research/publication/9866/"
}

Documents

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